This invention relates generally to dynamic random access memory (DRAM) cell devices and particularly relates to a realistic formation method for such devices which does not require poor step coverage of the thin films employed.
Continued growth in the capacity of dynamic random access memory (DRAM) technology can be enhanced by minimizing the size of individual DRAM cells. As technology develops, DRAM devices need to store more bits of information, use less power per bit of stored information and have the individual memory cells containing the stored bits occupy less area on the semiconductor chip. The smallest theoretical limit of a memory cell is four times the square of the feature size on a chip, or 4F2 where F represents minimum feature size. The feature size is the minimum width of the electrical leads or wiring and minimum spacing between wiring on the chip. Each cell comprises a MOS pass transistor and a storage capacitor.
A memory cell which achieves this type of minimum size is known as a cross point cell. The name xe2x80x9ccross point cellxe2x80x9d is derived from the location of the cell in an array of cells at the point where one word line and one bit line cross each other. Such cells normally employ an open bit line architecture. The open bit line architecture can result in detrimental substrate noise coupling into the bit lines, and can require an excessive number of masks to form the cross point cell.
In an effort to address these problems, the invention described in U.S. patent application Ser. No. 08/934,157 was developed. The Ser. No. 08/934,157 application is expressly incorporated herein by reference, and is co-assigned to Texas Instruments Incorporated. Although the DRAM cell and manufacturing method disclosed in the referenced application are quite promising, the formation method in the referenced application depends on deliberately obtaining poor step coverage of certain materials during the fabrication process. In particular, poor step coverage was desired at the bottom of holes during fabrication of the structures. It is difficult to obtain consistent manufacturing quality when the method requires deliberately seeking poor step coverage.
Further, in the prior art exemplified in the Ser. No. 08/934,157 application, each functional part of the cross point DRAM cell is formed as a portion of a symmetrical pillar. Therefore, each element has a double layer, due to the symmetry of the cell about a center line. Accordingly, to minimize the cell dimensions, the thickness of each layer had to be quite thin, resulting in added manufacturing difficulties.
Therefore, a need has arisen for a realistic method of forming a cross point type DRAM cell which does not depend on poor step coverage of the thin films, and which can be formed in an asymmetric fashion so that each element of the cell need not be divided into two excessively thin layers. The present invention provides such a realistic formation method of the cross point type DRAM cell wherein the process does not depend on poor step coverage of the thin films. Further, each individual DRAM cell can be formed in an asymmetric fashion with more realistic thicknesses for the various components which are employed.
In accordance with the present invention, a dynamic random access memory (DRAM) device comprises a substrate of semiconductor material having a main outer surface; a plurality of substantially parallel word lines which are located outwardly of the main outer surface of the substrate; and a plurality of substantially parallel bit lines which are also located outwardly of the main outer surface of the substrate. Each of the word lines has a word line width defined by first and second word line edges and is separated from adjacent word lines by a word line separation distance. Similarly, each of the bit lines has a bit line width defined by first and second bit line edges and is separated from adjacent bit lines by a bit line separation distance. The bit lines are substantially perpendicular to the word lines.
The device further comprises a plurality of memory cells each associated with an intersection of a given one of the fist and second world line edges of a given one of the word lines and a given one of the first and second bit line edges of a given one of the bit lines. Each of the memory cells in turn comprises a pillar of semiconductor material; a storage node; a storage node plug; a bit line plug; and a word line plug. The pillar of semiconductor material extends outward from the main outer surface of the substrate and is electrically isolated from adjacent memory cells. The pillar has a pillar outer surface and includes an active region of the semiconductor material which is substantially centered inward of the intersection. The pillar is formed with a hole region which is defined by a hole floor and at least one hole wall. The hole floor is located outwardly of the main outer surface of the substrate.
The storage node is offset from the active region of the pillar in a direction away from the given one of the word lines and the given one of the bit lines. The storage node plug extends from the storage node, through the hole region in the pillar, to contact the hole floor and to form thereat a storage node contact and one of a drain and a source of a MOS transistor. The storage node plug is electrically isolated from the at least one hole wall.
The bit line plug extends from the given one of the bit lines inwardly to contact the pillar outer surface and to form thereat a bit line contact and the other of the drain and the source of the MOS transistor. The word line plug extends from the given one of the word lines through the hole region in the pillar and terminates outwardly of the hole floor. The word line plug is electrically isolated from the semiconductor material of the pillar, such that a portion of the word line plug adjacent to and electrically isolated from the semiconductor material of the pillar forms a gate of the MOS transistor. A corresponding portion of the semiconductor material of the pillar forms a channel region of the MOS transistor.
In accordance with the present invention, a method for manufacturing a dynamic random access memory device comprises the steps of providing a substrate of semiconductor material; forming a plurality of pillars of semiconductor material extending outward from the substrate; forming a plurality of substantially parallel bit lines; interconnecting the bit lines with outer surfaces of the pillars via a plurality of bit line plugs; forming at least one hole region in each of the plurality of pillars; forming a plurality of substantially parallel word lines; locating a word line plug in each of the hole regions; forming a plurality of storage nodes; and interconnecting the storage nodes with the floors of the hole regions in the pillars via a plurality of storage node plugs. The substrate of semiconductor material which is provided can have a main outer surface. The pillars can extend outwardly from the main outer surface of the substrate, and each of the pillars can have a pillar outer surface. The pillars can be formed using a first mask, and can be electrically isolated from each other. The pillars can include an active region of the semiconductor material.
In the step of forming the plurality of substantially parallel bit lines, the bit lines can be located outwardly of the main outer surface of the substrate, and each of the bit lines can have a bit line width defined by first and second bit line edges. Further, each of the bit lines can be separated from adjacent bit lines by a bit line separation distance. The bit lines can be formed using a second mask.
In the step of interconnecting the bit lines with the pillar outer surfaces via the bit line plugs, the result can be the formation of a plurality of bit line contacts and one of drains and sources of a plurality of MOS transistors at the intersections of the bit line plugs with the pillar outer surfaces. In the step of forming the at least one hole region, the region can be defined by a hole floor and at least one hole wall. Such a hole region can be formed in each of the plurality of pillars, and the hole floors can be located outwardly of the main outer surface of the substrate.
In the step of forming the plurality of substantially parallel word lines, the word lines can be located outwardly of the main outer surface of the substrate, and each of the word lines can have a word line width defined by first and second word line edges. Further, each of the word lines can be separated from adjacent word lines by a word line separation distance. The word lines can be substantially perpendicular to the bit lines, and the word lines can be formed using a third mask. A given one of the first and second word line edges of a given one of the word lines and a given one of the first and second bit line edges of a given one of the bit lines can intersect substantially outward of the center of a given one of the active regions.
In the step of locating the word line plug in each of the hole regions, each of the word line plugs can extend from a corresponding adjacent one of the word lines inwardly into the hole region and can terminate outward of the hole floor. Each of the word line plugs can be electrically isolated from the semiconductor material of the pillar, such that a portion of each of the word line plugs adjacent to and electrically isolated from the semiconductor material of the pillar forms a gate of the MOS transistor, with the corresponding portion of the semiconductor material of the pillar forming a channel region of the MOS transistor.
In the step of forming the plurality of storage nodes, one node can be formed for each of the active regions, and each of the storage nodes can be offset from the corresponding one of the active regions in a direction away from the given one of the word lines and the given one of the bit lines which intersect substantially outwardly of the center of the given one of the active regions. The storage nodes can be formed using a fourth mask.
Finally, in the step of interconnecting the storage nodes with the hole floors of the pillars via the plurality of storage node plugs, the interconnection can be conducted such as to form a plurality of storage node contacts and the other of sources and drains of the plurality of MOS transistors at the intersections of the storage node plugs with the hole floors. The storage node plugs can extend through the hole regions in the pillars and can be electrically isolated from the hole walls and the word line plugs.
Technical advantages of the present invention include a formation process which can be carried out with existing process technologies, and which does not depend on deliberate poor step coverage of the thin films. Further, the formation process is enhanced since the symmetrical structure of the prior art cell, with concomitant excessively thin layers, is done away with. However, significant technical advantages of the prior-art Ser. No. 08/934,157 application are retained, including minimization of transmission of substrate noise to the bit line and a reduced number of masks (four) required for fabrication.
Other technical advantages of the present invention will be readily apparent to one skilled in the art from the following figures, descriptions, and claims.